As memory circuits have become increasingly integrated, the design rule for their fabrication has decreased from approximately 1 .mu.m for conventional 1-Mbit DRAMs to approximately 0.15 .mu.m for 1-Gbit DRAMs. As the design rule has decreased, there has generally been a corresponding decrease in the size of contact holes used to access the transistor regions in the substrate upon which the word and bit lines of the memory device are formed.
In stacked capacitor DRAMs, three-dimensional capacitor structures typically are formed in such contact holes. The aspect ratio of the contact holes is typically high, as the contact hole typically passes through word and bit line layers, as well as intervening insulation regions. With increased integration of the transistor cells in the device, the aspect ratio generally increases. The increased aspect ratio may make it difficult to fabricate the contact holes for the transistor cells using conventional photolithographic techniques without misaligning the holes with respect to the transistor structures. Thus, alignment tolerance is an important factor in the producibility of submicron design rule transistor cells.
FIG. 1 is a sectional view of a conventional DRAM cell, including a bit line 16 with a capping insulating layer 17, a semiconductor substrate 10, a field region 12, a source region 13, an interlayer dielectric 18, a spacer 21, and a storage electrode 23. As illustrated, when conventional photo-lithographic techniques are employed to pattern a contact hole for the storage electrode 23, the contact hole pattern may be misaligned, causing a portion 17A of the bit line 16 to be exposed. When the storage electrode 23 is formed, the exposed bit line portion 17A may electrically contact the storage electrode 23, causing failure of the memory device.
Similar misalignment problems may occur with respect to word lines. FIG. 2 is a cross-sectional view of a the conventional DRAM cell of FIG. 1, along the bit line, illustrating a polycide word line 26 with a capping insulating layer 27, and a spacer 21. Here, because the contact hole pattern typically is more closely aligned with respect to the upper layers of the device than with respect to the lower layers of the device, a word line 26 and a source region 13 removed from the top surface of the substrate may be significantly misaligned with respect to the contact hole pattern. Upon etching, misalignment of the pattern may cause a portion 26A of the bit line 26 to be exposed, allowing an undesirable electrical contact between the bit line 26 and the storage electrode 23 subsequently formed in the contact hole. In addition, the misalignment may reduce the contact area accessible on the source region 13. Although forming spacers on the side of the contact hole may help improve alignment tolerance, if misalignment is sufficient, the storage electrode 23 may still contact active portions of the word and bit lines.